Modern electronic systems, which include a multiple of devices such as high-performance microprocessor and programmable logic devices, increasingly require a plurality of voltage levels. Care must be taken to power up and down the corresponding voltage rails that supply these voltages. Internal circuits suffer stress if certain power rails are active while others are inactive. In addition, microprocessors may suffer latch-up, which damages or destroys affected transistors. To prevent these problems, the multiple devices must be powered up and powered down in a proper sequence.
Power supply sequence controllers enable system designers to meet the need for power sequencing in their designs. A programmable sequence controller may include programmable logic that a user programs according to the particular power sequence control desired. An example programmable sequence controller is disclosed in U.S. Pat. No. 6,735,706, which is hereby incorporated by reference in its entirety.
A user will typically need to configure a programmable sequence controller and the devices it sequences. One very popular technique to configure and test electronic systems is known as boundary scan (BSCAN). Boundary scan techniques are standardized according to specifications such as IEEE-1149.1, also known as JTAG (Joint Test Action Group). In a JTAG or boundary-scan-enabled device, each input and output signal is supplemented with a multi-purpose memory element denoted as a boundary-scan cell. These cells are configured as a parallel-in, parallel-out shift register. The shift registers thus formed in each device or integrated circuit (IC) in the system are serially-connected in a daisy chain fashion such that test vectors may be shifted into and results shifted out of the system.
As part of the standardized boundary scan technique, each IC is required to include a JTAG port for access to the boundary-scan cells. Each JTAG port must, at a minimum, provide pins or I/O pads for the following signals: Test Data in (TDI), Test Data Out (TDO), Test Clock (TCK), and Test Mode Select (TMS). These pins or pads are coupled to a header on the circuit board (often denoted as a BSCAN or JTAG header) holding the IC. If there are multiple devices on a circuit board, they may be daisy-chained together to form a scan chain connected to the BSCAN header. One example of such an arrangement for programmable logic devices is shown and described in U.S. Pat. No. 5,635,855, which is hereby incorporated by reference. The configuration of BSCAN headers has been standardized into either a single row of eight pins or two rows of five pins each. To access the boundary-scan cells in a JTAG-enabled IC, a user physically couples a JTAG test cable to the BSCAN header on the board. But note the problem that arises if a BSCAN chain were to contain a programmable sequencer and the devices it controls. The programmable sequencer must be programmed before it is operational to supply power to the devices it controls. These other devices, lacking power, would thus not be active in the chain, and the chain would effectively be broken.
The conventional approach to this problem is to provide two BSCAN headers on the circuit board: one connected to the sequencer and the other connected to a BSCAN chain containing the devices controlled by the sequencer. Once the sequencer has been programmed through one BSCAN header and is supplying power to the other devices, the devices are programmed or tested through the other BSCAN header. However, the second BSCAN header increases costs and consumers scarce circuit board area.
Accordingly, there is a need in the art for a more effective approach for enabling the programming and/or testing of multiple devices in a scan chain that are operable at different times.